The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that reduces a test time for operation of the semiconductor memory device with high capacity, and a testing method of the semiconductor memory device.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data according to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into memory cells selected by addresses.
As the operating speed of the system increases and semiconductor integrated circuit technologies are advanced, semiconductor memory devices are required to input and output data at higher speed. In order for faster and stable operation of semiconductor memory devices, a variety of circuits inside the semiconductor memory devices must be able to operate at a high speed and transfer signals or data between the circuits at a high speed. This causes a design and fabrication of a semiconductor memory device to be complex, and also causes a testing process of the fabricated semiconductor memory device to be complex and difficult. More specifically, the number of operations to be tested increases, and a testing procedure for each operation is also complicated. The testing process of a semiconductor memory device with high capacity and integration degree requires a complex algorithm and much test time due to its complexity. Accordingly, it takes a long time to test a semiconductor memory device using a method of accessing the semiconductor memory device from the outside and testing it by an automatic test equipment (ATE), which has been typically used. Consequently, this typical method leads to a decrease in productivity of a semiconductor memory device as well as test efficiency.
Therefore, there is increasing difficulty in mass-producing a semiconductor memory device, and thus many attempts have been made to prevent a decrease in productivity. To overcome such a difficulty, new testing methods, which can replace a typical testing process of requiring a long test time, have been proposed to reduce a test time and cost. For example, one of new testing methods is a test during burn-in (TDBI) process performed after packaging a semiconductor memory device. The TDBI process is a test process of applying a stress to determine whether there is a defect or not by repeating a write operation of a simple pattern on the semiconductor memory device that is packaged. Specifically, the TDBI process is a test process of applying a stress to the semiconductor memory device by performing a write operation of a simple pattern for a long time (maximally, several hours) at a relatively high temperature (maximally, approximately 100° C.) under a relatively high voltage after a packaging process. Since the TDBI process is performed at a package level, excessive current consumption sometimes causes package balls to be melted to thereby damage a test equipment including a probe card, leading to an increase in test cost. Accordingly, a typical semiconductor memory device should be operated within a range so as to consume the amount of current not exceeding a predetermined amount.
In this way, to prevent the package from being damaged due to overcurrent during TDBI process, semiconductor memory devices to be simultaneously tested should be limited in number, and word lines to be simultaneously enabled in each semiconductor memory device through one-time active command is also limited in number. Resultingly, most of time to be taken for a subsequent process is used in the TDBI process, and thus it is possible to disperse various tests for a semiconductor memory device. However, the TDBI process is not effective to reduce a test time notably.
To test a semiconductor memory device more effectively before packaging, a testing method has been proposed where a built-in self-test (BIST) circuit is built in the semiconductor memory device. In addition, to increase yield of a semiconductor memory device, another testing method has been introduced where a built-in self-repair (BISR) is built in the semiconductor memory device so as to repair defects detected through a wafer level burn-in (WBI) test, and this method is increasingly applied to various fields. Herein, The BISR of the semiconductor memory device is accompanied with a variety of mechanisms such as built-in self-diagnostics (BISD), built-in redundancy analysis (BIRA) as well as BIST.
This BIST suggested an alternative to solve problems, e.g., limitation in channel, in the case of a testing process using a conventional ATE. Since a test control circuit, which is capable of realizing a memory test algorithm, is built in the BIST circuit, a great number of ports for a channel to be connected to an external test equipment are not required, and operation of the semiconductor memory device can be tested at a high speed. The conventional BIST determines whether there is a defect or not, in such a way that commands, addresses and data are generated according to a test pattern, then written to a unit cell, and read out through a comparator. If there is a defect, the conventional BIST determines whether the defect can be repaired using a redundancy circuit.
However, a defect may occur in a unit cell of a semiconductor memory device in various circumstances besides read and write operations. If a variety of test patterns and algorithms are incorporated in an internal circuit for BIST in consideration of such various circumstances, a total area of the semiconductor memory device may be unfavorably increased. Therefore, a testing process as to whether defects may occur in various operating circumstances is performed in a TDBI process after fabrication of a semiconductor memory device package. As described above, however, there is a disadvantage in that it takes a long time to test a semiconductor memory device in a TDBI process.